Programming help for Verilog beginner. Debugging in ISE -

i have experience in vhdl , systemc, , i'm training learn verilog, i'm having trouble getting started.

i'm trying make 8 bit adder.

module alu( input [7:0] a, input [7:0] b, input clk, input op, output reg [7:0] out, output reg overflow );  integer mya; integer myb;  @(negedge clk) begin mya = a; myb = b; overflow = 0;  if (op == 0) begin     //subtract     out = mya - myb;     if (mya - myb <0) begin         overflow = 1;     end end  else begin     //add     out = mya + myb;     if (mya + myb  > 255) begin         overflow = 1;         end     end  end  endmodule 

but in testing doesn't work properly.

i used ise generate test bench, , since don't know how setup clock, set manually:

// add stimulus here     = 255;     b = 45;     clk = 1;     op = 1;     #100     clk = 0;      // add stimulus here     = 0;     b = 255;     clk = 1;     op = 1;     #100     clk = 0;      // add stimulus here     = 255;     b = 0;     clk = 1;     op = 0;     #100     clk = 0;      // add stimulus here     = 90;     b = 45;     clk = 1;     op = 1;     #100     clk = 0; 

the last instruction, 45+90 gives me correct result, every other result gives me 0.

i've tried several variations of main if, there errors in output.

if (op == 0) begin   out = + b; if (mya-myb <0) begin   //overflow   out = 7; end end else begin   out = a-b;    if (mya+myb>255) begin     //overflow     out = 8;    end end 

here's full test bench code. edited include #100 between clk = 0 , clk = 1.

`timescale 1ns / 1ps  module a;  // inputs reg [7:0] a; reg [7:0] b; reg clk; reg op;  // outputs wire [7:0] out;  // instantiate unit under test (uut) alu uut (     .a(a),      .b(b),      .clk(clk),      .op(op),     .out(out) );  initial begin     // initialize inputs     = 0;     b = 0;     clk = 0;     op = 0;      // wait 100 ns global reset finish     #100;      // add stimulus here     = 55;     b = 45;     clk = 1;     op = 1;     #100     clk = 0;     #100      // add stimulus here     = 255;     b = 45;     clk = 1;     op = 1;     #100     clk = 0;     #100      // add stimulus here     = 0;     b = 255;     clk = 1;     op = 1;     #100     clk = 0;     #100      // add stimulus here     = 255;     b = 0;     clk = 1;     op = 0;     #100     clk = 0;     #100      // add stimulus here     = 90;     b = 45;     clk = 1;     op = 1;     #100     clk = 0;     #100 end  endmodule 

#x in verilog means "delay x time steps before continuing". in code

#100 clk = 0;  // add stimulus here = 255; b = 0; clk = 1; 

there's no delay between clock going low , going high again, might problem. try adding #100 somewhere between clk = 0; , clk = 1;