altera - VHDL - direct instantiation for PLL -

i trying make vga controller on de0 board , have made following code:

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;  entity vga  port (clk                       :   in   std_logic;         vga_hs, vga_vs          :   out std_logic;         vga_r, vga_g, vga_b :   out std_logic_vector(3 downto 0)); end entity vga;  architecture a1 of vga signal rst, clk25   :   std_logic; begin sync1   :   entity work.sync(a1)             port map (clk25, vga_hs, vga_vs, vga_r, vga_g, vga_b); clk_25  :   entity work.pll(rtl)             port map (clk, rst, clk25);  end architecture a1; 

when compile model following error message:

error (12006): node instance "altpll_0" instantiates undefined entity "pll_altpll_0"

i'm instantiating 2 components first sync1 synchronisation counts 640 x 480 display second (clk_25) pll clock generated quartus ii. following model:

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;  entity pll port (     clk_clk    : in  std_logic := '0'; --    clk.clk     rst_reset  : in  std_logic := '0'; --    rst.reset     clk_25_clk : out std_logic         -- clk_25.clk ); end entity pll;  architecture rtl of pll component pll_altpll_0     port (         clk       : in  std_logic                     := 'x';             --    clk         reset     : in  std_logic                     := 'x';             -- reset         read      : in  std_logic                     := 'x';             -- read         write     : in  std_logic                     := 'x';             -- write         address   : in  std_logic_vector(1 downto 0)  := (others => 'x'); -- address         readdata  : out std_logic_vector(31 downto 0);                    -- readdata         writedata : in  std_logic_vector(31 downto 0) := (others => 'x'); -- writedata         c0        : out std_logic;                                        -- clk         areset    : in  std_logic                     := 'x';             -- export         locked    : out std_logic;                                        -- export         phasedone : out std_logic                                         -- export     ); end component pll_altpll_0;  begin  altpll_0 : component pll_altpll_0     port map (         clk       => clk_clk,    --       inclk_interface.clk         reset     => rst_reset,  -- inclk_interface_reset.reset         read      => open,       --             pll_slave.read         write     => open,       --                      .write         address   => open,       --                      .address         readdata  => open,       --                      .readdata         writedata => open,       --                      .writedata         c0        => clk_25_clk, --                    c0.clk         areset    => open,       --        areset_conduit.export         locked    => open,       --        locked_conduit.export         phasedone => open        --     phasedone_conduit.export     );  end architecture rtl; -- of pll 

how can directly instantiate pll(rtl) working library ?

generate pll megawizard in quartus prime, , include generated .qip file in design. assume megawizard used generate pll_altpll_0 in example.

the generated pll entity compiled work (or library shown in .qip file), , can instantiate pll entity instantiation, , leave out redundant component declaration in architecture uses generated pll. code like, assuming workpll_altpll_0 compiled work library:

altpll_0 : entity work.pll_altpll_0   port map (