string - Systemverilog: Is there a way to make signal unique in macro instantiating a module? -

i have macro this:

`define bob_stage(_bus_in, _bus_out) \    bob_module auto_``_bus_out``_bob_module ( .bus_in(_bus_in), .bus_out(_bus_out) ); 

(notice _bus_out becomes part of instance name make unique instances.)

so these used on place , take concatenated signals in 1 signal out, out signal indexed.

example use:

`bob_stage( {a,b,c,d}, out[1] ); 

the problem both concat {} , index [] mess automatic assignment in module instance name.

i want solve without adding input signal name , without temporary signals on outside of macro.

is there way convert output signal name index unique string... such $sformatf , replace index brackets underscores?

or there other way uniqify signal name keep legal? atoi() make unique number based off signal name?

you can escape name allow symbols in identifier

`define bob_stage(_bus_in, _bus_out) \    bob_module \auto_``_bus_out``_bob_module ( .bus_in(_bus_in), .bus_out(_bus_out) );  `bob_stage( {a,b,c,d}, out[1] ); 

will become

bob_module \auto_out[1]_bob_module ( .bus_in(_bus_in), .bus_out(_bus_out) ); 

this limit of can creating identifiers in systemverilog.