system verilog - What is the implication of not resetting a register in reset aware always_ff block? -

what consequence of not resetting flop inside reset aware alaways_ff block?

example 1:

always_ff @(posedge clk, negedge rst) begin    if (~rst) begin       reg_a <='0;       reg_b <='0;    end else begin       if (condition_1) begin          reg_a <= some_signal;       end else if (condition_2) begin          reg_b <= signal;       end    end end 

example 2:

always_ff @(posedge clk, negedge rst) begin    if (~rst) begin       reg_a <='0;    end else begin       if (condition_1) begin          reg_a <= some_signal;       end else if (condition_2) begin          reg_b <= signal;       end    end end 

the difference between example 1 , 2 is, in example 2, reg_b doesn't have reset condition. consequence of mistake in backend/synthesis? i've front end rtl design background little experience in sylthesis. so, i'm trying understand why example 2 above bad practice.

one obvious problem is- after reset reg_b x in example 2. if reg_b used in control logic might introduce bug in design. other other problem can create?

i not think cause error during synthesis or pnr.
on huge designs did encountered ff not reseted. can avoid unnecessary constraints on pnr tools.
said however, should careful not introduce bugs using before written 'x' until then.